Field
Aspects of the present disclosure relate generally to power delivery networks (PDNs), and in particular, to a system and method for reducing the complexity of PDNs through the use of local power multiplexers.
Background
Often an integrated circuit (IC), such as a system on chip (SOC), includes multiple power rails for independently providing supply voltages to various cores of the IC. A set of regulators are typically provided to generate the supply voltages for the cores.
The voltage level of the supply voltage applied to a core depends on the particular operation performed by the core. If the core is performing a demanding operation (e.g., processing substantial amount of data at a fast rate), the supply voltage applied to the core is relatively high. If, on the other hand, the core is performing a not-so-demanding operation (e.g., simply retaining data in memory cells), the supply voltage applied to the core is relatively low.
In addition, the power rails that provide the supply voltages to the respective cores need to be sized to supply the needed current for the cores. As all the cores may need to perform demanding operations, the power rails need to be sized to handle the worst case or highest current required by the cores. If there are multiple power rails in an IC, and each of the power rails need to be designed for the worst case highest current, the amount of area needed to implement the multiple power rails may be substantially large.
Thus, there is a need to reduce the overall or aggregate size of the power rails, while still providing the currents or power needed by the various cores.